1. Field of the Invention
This invention relates to high speed parallel byte shifters for bus architecture data processing systems of the type described in my copending application Ser. No. 219,768 filed Dec. 23, 1980 for a "High Speed Byte Shifter." More particularly, this invention relates to error checking circuits for high speed parallel byte shifters.
2. Description of the Prior Art
Error checking and error correcting are necessary functions of modern data processing systems. Numerous sophisticated codes have been devised which not only assure detection of an error during data transfer from one register or storage device to another but provide means for correcting single and double bit errors. Single bit errors are the most common type of error and are easily detected by a parity bit which accompanies the data during transfer. For example, it is standard practice to provide one parity bit for every eight data bits in a nine bit byte.
When data is being shifted in a bit shifter or a byte shifter, a parity check will not determine if the correct byte has been selected or if it has been properly shifted in and out of the byte shifter.
Data processing systems which transfer data bytes in parallel also transfer the parity bit in parallel with the data. The parity bit provides means for checking or verifying the most common type of error which is the change of one data bit in the data byte. When the bytes of data are being shifted in parallel, the parity bit error detection does not detect a shift error nor does the parity bit detect that the byte being transferred from the data bus to a byte shifter is, in fact, the byte which should be selected for shifting. After a byte has been selected for shifting from a data bus, it must be returned to the data bus in shifted form. Prior art byte shifters have not treated the problem of byte selection error or shifted byte transfer error which could occur in byte shifters.
Data processing systems which employ data bus architecture also employ input and output registers to present and receive bytes and words of data information on the data bus. Byte shifters must take byte data from the data bus and return it after it has been processed. Even if the byte shifter is operable to effect the proper shift operation on the proper byte, the parity check bit of the data byte cannot be employed as a means to check that the shifted byte in the byte shifter is transferred to the proper input or output register of the data bus. If the byte in the data bus register is not changed by loading a new byte, the old byte which remains unchanged still has a proper parity bit, thus, absence of a proper transfer or loading of the new byte is not detected.
It is generally recognized that errors in data processing systems are more likely to occur when data as signals are being transferred between registers. When byte shifters are employed which are not hard wired, the probability of error increases greatly. When byte shifters are employed, that utilize complex logic and large number of gates in matrix form, the probability of an error increases. When the speed of operation of the data processing system is very high, the inclusion of complex circuitry not only slows down the operation of the byte shifter, but also increases the probability of data selection errors and data transfer errors.
It would be desirable to provide a high speed byte shifter which is adapted to be connected to a bus architecture high speed data processing system and which either avoids the problems of the prior art or provides a simple economical solution to avoid errors and increase the speed of operation.